
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   14:20:32 01/30/2011
-- Design Name:   RS232_TX
-- Module Name:   E:/test_PIC/tb_RS232_TX.vhd
-- Project Name:  test_PIC
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: RS232_TX
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_RS232_TX_vhd IS
END tb_RS232_TX_vhd;

ARCHITECTURE testbench OF tb_RS232_TX_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT RS232_TX
	PORT(
		clk : IN std_logic;
		Reset : IN std_logic;
		Start : IN std_logic;
		Data : IN std_logic_vector(7 downto 0);          
		EOT : OUT std_logic;
		TX : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL Reset :  std_logic := '0';
	SIGNAL Start :  std_logic := '0';
	SIGNAL Data :  std_logic_vector(7 downto 0) := (others=>'0');

	--Outputs
	SIGNAL EOT :  std_logic;
	SIGNAL TX :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: RS232_TX PORT MAP(
		clk => clk,
		Reset => Reset,
		Start => Start,
		Data => Data,
		EOT => EOT,
		TX => TX
	);

	p_clk : PROCESS
  BEGIN
     Clk <= '1', '0' after 25 ns;
     wait for 50 ns;
  END PROCESS;

END testbench;
